{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1556438907317 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1556438907333 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 28 16:08:27 2019 " "Processing started: Sun Apr 28 16:08:27 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1556438907333 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1556438907333 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Timer -c Timer " "Command: quartus_map --read_settings_files=on --write_settings_files=off Timer -c Timer" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1556438907333 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1556438908660 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_ONE_PROCESSOR" "" "Only one processor detected - disabling parallel compilation" {  } {  } 0 20029 "Only one processor detected - disabling parallel compilation" 0 0 "Analysis & Synthesis" 0 -1 1556438908660 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "timer.v 1 1 " "Found 1 design units, including 1 entities, in source file timer.v" { { "Info" "ISGN_ENTITY_NAME" "1 Timer " "Found entity 1: Timer" {  } { { "Timer.v" "" { Text "E:/My_design/Timer/Timer.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1556438935790 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1556438935790 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "Timer " "Elaborating entity \"Timer\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1556438935993 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 25 Timer.v(23) " "Verilog HDL assignment warning at Timer.v(23): truncated value with size 32 to match size of target (25)" {  } { { "Timer.v" "" { Text "E:/My_design/Timer/Timer.v" 23 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1556438936000 "|Timer"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 Timer.v(49) " "Verilog HDL assignment warning at Timer.v(49): truncated value with size 32 to match size of target (1)" {  } { { "Timer.v" "" { Text "E:/My_design/Timer/Timer.v" 49 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1556438936000 "|Timer"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 Timer.v(50) " "Verilog HDL assignment warning at Timer.v(50): truncated value with size 32 to match size of target (7)" {  } { { "Timer.v" "" { Text "E:/My_design/Timer/Timer.v" 50 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1556438936000 "|Timer"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 Timer.v(54) " "Verilog HDL assignment warning at Timer.v(54): truncated value with size 32 to match size of target (7)" {  } { { "Timer.v" "" { Text "E:/My_design/Timer/Timer.v" 54 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1556438936000 "|Timer"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 Timer.v(59) " "Verilog HDL assignment warning at Timer.v(59): truncated value with size 32 to match size of target (4)" {  } { { "Timer.v" "" { Text "E:/My_design/Timer/Timer.v" 59 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1556438936000 "|Timer"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 Timer.v(60) " "Verilog HDL assignment warning at Timer.v(60): truncated value with size 32 to match size of target (4)" {  } { { "Timer.v" "" { Text "E:/My_design/Timer/Timer.v" 60 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1556438936000 "|Timer"}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "2 " "Inferred 2 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Mod0\"" {  } { { "Timer.v" "Mod0" { Text "E:/My_design/Timer/Timer.v" 59 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1556438936699 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Div0\"" {  } { { "Timer.v" "Div0" { Text "E:/My_design/Timer/Timer.v" 60 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1556438936699 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1556438936699 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_divide:Mod0 " "Elaborated megafunction instantiation \"lpm_divide:Mod0\"" {  } { { "Timer.v" "" { Text "E:/My_design/Timer/Timer.v" 59 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1556438936843 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_divide:Mod0 " "Instantiated megafunction \"lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 7 " "Parameter \"LPM_WIDTHN\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1556438936843 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1556438936843 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1556438936843 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1556438936843 ""}  } { { "Timer.v" "" { Text "E:/My_design/Timer/Timer.v" 59 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1556438936843 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_72m.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_72m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_72m " "Found entity 1: lpm_divide_72m" {  } { { "db/lpm_divide_72m.tdf" "" { Text "E:/My_design/Timer/db/lpm_divide_72m.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1556438936926 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1556438936926 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_akh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_akh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_akh " "Found entity 1: sign_div_unsign_akh" {  } { { "db/sign_div_unsign_akh.tdf" "" { Text "E:/My_design/Timer/db/sign_div_unsign_akh.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1556438936981 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1556438936981 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_qse.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_qse.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_qse " "Found entity 1: alt_u_div_qse" {  } { { "db/alt_u_div_qse.tdf" "" { Text "E:/My_design/Timer/db/alt_u_div_qse.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1556438937018 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1556438937018 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_divide:Div0 " "Elaborated megafunction instantiation \"lpm_divide:Div0\"" {  } { { "Timer.v" "" { Text "E:/My_design/Timer/Timer.v" 60 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1556438937064 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_divide:Div0 " "Instantiated megafunction \"lpm_divide:Div0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 32 " "Parameter \"LPM_WIDTHN\" = \"32\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1556438937064 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1556438937064 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1556438937064 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1556438937064 ""}  } { { "Timer.v" "" { Text "E:/My_design/Timer/Timer.v" 60 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1556438937064 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_ibm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_ibm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_ibm " "Found entity 1: lpm_divide_ibm" {  } { { "db/lpm_divide_ibm.tdf" "" { Text "E:/My_design/Timer/db/lpm_divide_ibm.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1556438937161 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1556438937161 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_olh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_olh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_olh " "Found entity 1: sign_div_unsign_olh" {  } { { "db/sign_div_unsign_olh.tdf" "" { Text "E:/My_design/Timer/db/sign_div_unsign_olh.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1556438937194 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1556438937194 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_mve.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_mve.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_mve " "Found entity 1: alt_u_div_mve" {  } { { "db/alt_u_div_mve.tdf" "" { Text "E:/My_design/Timer/db/alt_u_div_mve.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1556438937284 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1556438937284 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1556438937959 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1556438938599 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1556438938599 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "226 " "Implemented 226 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1556438938737 ""} { "Info" "ICUT_CUT_TM_OPINS" "15 " "Implemented 15 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1556438938737 ""} { "Info" "ICUT_CUT_TM_LCELLS" "207 " "Implemented 207 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1556438938737 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1556438938737 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 7 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4826 " "Peak virtual memory: 4826 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1556438938773 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 28 16:08:58 2019 " "Processing ended: Sun Apr 28 16:08:58 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1556438938773 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:31 " "Elapsed time: 00:00:31" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1556438938773 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:26 " "Total CPU time (on all processors): 00:00:26" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1556438938773 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1556438938773 ""}